NXP Semiconductors /LPC43xx /ETHERNET /DMA_STAT

Transmit interrupt This bit indicates that frame transmission is finished and TDES1[31] is set in the First Descriptor.

Transmit process stopped This bit is set when the transmission is stopped.

Transmit buffer unavailable This bit indicates that the Next Descriptor in the Transmit List is owned by the host and cannot be acquired by the DMA. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing transmit descriptors, the host should change the ownership of the bit of the descriptor and then issue a Transmit Poll Demand command.

Transmit jabber timeout This bit indicates that the Transmit Jabber Timer expired, meaning that the transmitter had been excessively active. The transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.

Receive overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to application, the overflow status is set in RDES0[11].

Transmit underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.

Receive interrupt This bit indicates the completion of frame reception. Specific frame status information has been posted in the descriptor. Reception remains in the Running state.

Receive buffer unavailable This bit indicates that the Next Descriptor in the Receive List is owned by the host and cannot be acquired by the DMA. Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor was owned by the DMA.

Received process stopped This bit is asserted when the Receive Process enters the Stopped state.

Receive watchdog timeout This bit is asserted when a frame with a length greater than 2,048 bytes is received (10,240 when Jumbo Frame mode is enabled).

Early transmit interrupt This bit indicates that the frame to be transmitted was fully transferred to the MTL Transmit FIFO.

Reserved

Fatal bus error interrupt This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is set, the corresponding DMA engine disables all its bus accesses.

Early receive interrupt This bit indicates that the DMA had filled the first data buffer of the packet. Receive Interrupt bit 6 in this register automatically clears this bit.

Abnormal interrupt summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 1: Transmit process stopped DMA_STAT register, bit 3: Transmit jabber timeout DMA_STAT register, bit 4: Receive overflow DMA_STAT register, bit 5: Transmit underflow DMA_STAT register, bit 7: Receiver buffer unavailable DMA_STAT register, bit 8: Receive process stopped DMA_STAT register, bit 9: Receive watchdog timeout DMA_STAT register, bit 10: Early transmit interrupt DMA_STAT register, bit 13: Fatal bus error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared.

Normal interrupt summary Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_INT_EN register: DMA_STAT register, bit 0: Transmit interrupt DMA_STAT register, bit 2: Transmit buffer unavailable DMA_STAT register, bit 6: Receive interrupt DMA_STAT register, bit 14: Early receive interrupt Only unmasked bits affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes NIS to be set is cleared.

Receive Process State These bits indicate the receive DMA state machine state. This field does not generate an interrupt. 000 = Stopped: Reset or Stop Receive Command issued. 001 = Running: Fetching Receive Transfer Descriptor. 010 = Reserved. 011 = Running: Waiting for receive packet. 100 = Suspended: Receive Descriptor Unavailable. 101 = Running: Closing Receive Descriptor. 110 = TIME_STAMP write state. 111 = Running: Transferring the receive packet data from receive buffer to host memory.

Transmit Process State These bits indicate the transmit DMA state machine state. This field does not generate an interrupt. 000 = Stopped; Reset or Stop Transmit Command issued. 001 = Running; Fetching Transmit Transfer Descriptor. 010 = Running; Waiting for status. 011 = Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO). 100 = TIME_STAMP write state. 101 = Reserved. 110 = Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow. 111 = Running; Closing Transmit Descriptor.

Error bit 1 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during data transfer by TxDMA. 0 = Error during data transfer by RxDMA.

Error bit 2 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during read transfer. 0 = Error during write transfer.

Error bit 3 This bit indicates the type of error that caused a Bus Error (e.g., error response on the AHB interface). This bits is valid only when bit 13 in this register is set. This field does not generate an interrupt. 1 = Error during descriptor access. 0 = Error during data buffer access.

Reserved